1. Field of the Invention
The present invention relates generally to a phase comparator circuit, more particularly, to a phase comparator circuit for use in a clock regeneration PLL circuit to detect a lead or lag in clock signal phase relative to data signal edge and provide the detected signal through a loop filter to a voltage controlled oscillator (VCO).
2. Description of the Related Art
There are two types of phase comparator circuits; one is of an analog type outputting a signal proportional to a phase error detected and the other is of a digital type detecting a positive or negative polarity of a phase error. Since an offset component included in output of an analog phase comparator becomes problematic with increase in operating frequency, there has been a tendency that a digital phase comparator is adopted in a case where a phase error is desired to be the minimum.
FIG. 12 shows a prior art digital phase comparator circuit. FIGS. 13 and 14 are time charts showing operation of this circuit, wherein FIG. 13 shows a case where falling edges of a clock signal CLK lag corresponding edges of data signal DATA in phase while FIG. 14 shows a case where falling edges of the clock signal CLK lead corresponding edges of the data signal DATA in phase.
The data signal DATA is a non-return-to-zero (NRZ) signal and functions as a reference signal for the clock signal CLK which is regenerated from the data signal DATA. Clocks CLK and *CLK are in opposite phase with each other.
D flip-flops 10 and 11 detect logic levels of the data signal DATA on rises of the respective clock signals CLK and *CLK to hold the logic levels and give both outputs 10Q and 11Q thereof to an XOR (exclusive OR) gate 12. The output ED of the XOR gate 12 goes high when the outputs of the D flip-flops 10 and 11 are different in logic levels. The outputs 10Q and 11Q lag behind the data signal DATA and the time lag between the outputs 10Q and 11Q is equal to a half cycle time T/2 of the clock signal CLK, so each pulse of the signal ED has a width T/2 corresponding to an edge of the data signal DATA.
D flip-flops 13 and 14 detect logic levels of the signal ED on rising edges of the respective clock signals CLK and *CLK to output the result of the detection as an up signal UP and a down signal DWN, respectively.
When the phase comparator circuit of FIG. 12 is employed in a PLL circuit to raise the output frequency of a VCO by the up signal UP and lower it by the down signal DWN, the PLL circuit operates such that a falling edge of the clock signal CLK and an edge of the data signal DATA coincide with each other in timing.
Since the pulse width of the edge detection signal ED is equal to that of the clock signal CLK, the timing margins of the flip-flops 13 and 14 detecting logic levels of the signal ED at rising edges of the clock signals CLK and *CLK are comparatively short. When the frequency of the clock signal CLK is higher than, for example, 10 GHz, the waveform of the clock signal CLK comes close to a triangular. Furthermore, the data signal DATA has jitter. For such reasons, timing errors arise in the D flip-flops 13 and 14, having lead to a problem of hindrance in high-speed operation.